1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more specifically, to a non-volatile semiconductor memory device having a transistor passing current bidirectionally as a memory cell.
2. Description of the Background Art
Among non-volatile semiconductor memory devices, one type of flash EEPROM, namely an NROM (Nitride Read Only Memory) type flash EEPROM (hereinafter referred to as NROM) has been attracting attention. An NROM has an ONO (Oxide Nitride Oxide) film as a gate insulating film, and is capable of storing two bits of information per one memory cell. By employing the NROM, chip area per one bit may be reduced compared to other non-volatile semiconductor memory device having a floating gate. The NROM is disclosed in U.S. Pat. No. 6,081,456.
FIG. 10 is a circuit diagram related to an operation of applying potential to bit lines of a memory cell array of a conventional NROM.
Referring to FIG. 10, memory cell array 2 includes bit lines BL1 to BL5, word lines WL1 to WLn, memory cells 111 to 114 having their gates connected to the word line WL1, and memory cells 121 to 124 having their gates connected to the word line WLn.
In the memory cell array 2, among a row of memory cells sharing the same word line, adjacent memory cells share one bit line. Specifically, memory cells 111 and 112 are connected to a bit line BL2 at a node NB and thus share the bit line BL2. Memory cells 112 and 113 are connected to a bit line BL3 at a node NA and thus share the bit line BL3.
When using a current sensing type sense amplifier circuit 12 (hereinafter referred to as xe2x80x9ccurrent sense amplifier circuitxe2x80x9d), such as the one mounted on a conventional flash memory, with the memory cell array 2 thus structured, a switch circuit 504 switching potential applied to bit lines is structured as shown in FIG. 10.
The switch circuit 504 includes switch units 531 to 535 provided corresponding to bit lines BL1 to BL5, respectively.
The switch unit 531 includes an N-channel MOS transistor 542 connected between the read power source line 524, which is supplied with read power source potential VddR via the sense amplifier circuit 12, and the bit line BL1 for receiving a control signal VG1 at its gate. The switch unit 531 further includes an N-channel MOS transistor 544 connected between the ground power source line 522, which is supplied with ground potential GND, and the bit line BL1 for receiving a control signal GG1 at its gate.
The switch unit 532 includes an N-channel MOS transistor 552 connected between the read power source line 524 and the bit line BL2 for receiving a control signal VG2 at its gate, and an N-channel MOS transistor 554 connected between the ground power source line 522 and the bit line BL2 for receiving a control signal GG2 at its gate.
The switch unit 533 includes an N-channel MOS transistor 562 connected between the read power source line 524 and the bit line BL3 for receiving a control signal VG3 at its gate, and an N-channel MOS transistor 564 connected between the ground power source line 522 and the bit line BL3 for receiving a control signal GG3 at its gate.
The switch unit 534 includes an N-channel MOS transistor 572 connected between the read power source line 524 and the bit line BL4 for receiving a control signal VG4 at its gate, and an N-channel MOS transistor 574 connected between the ground power source line 522 and the bit line BL4 for receiving a control signal GG4 at its gate.
The switch unit 535 includes an N-channel MOS transistor 582 connected between the read power source line 524 and the bit line BL5 for receiving a control signal VG5 at its gate, and an N-channel MOS transistor 584 connected between the ground power source line 522 and the bit line BL5 for receiving a control signal GG5 at its gate.
Next, data writing/reading to/from the memory cell will be described. In the memory cell array shown in FIG. 10, each of two bit lines opposite to each other with a memory cell therebetween can be connected to either one of the ground power source line 522 or the read power source line 524. Such a structure allows to change the direction of voltage applied to the memory cell as desired. Each memory cell has two memory areas for enabling data writing/reading to/from different memory areas by changing the direction of the current. In the following, a description will be given focused on the memory cell 112 as a representative.
FIG. 11 is a diagram related to a data writing operation to a memory area L1 of the memory cell 112.
Referring to FIG. 11, potential of the bit line BL2 is set to the write potential VddW and potential of the bit line BL3 is set to the ground potential GND when writing data to the memory area L1. When the word line WL1 is activated to H level, which is the write state, write current Iw1 flows from the bit line BL2 to the bit line BL3 through the non-volatile memory cell 112. At this time, data is written to the memory area L1.
FIG. 12 is a diagram related to a data reading operation from a memory area L1 of the memory cell 112.
Referring to FIG. 12, the bit line BL3 receives the read power source potential VddR via current sense amplifier circuit 12 when reading data from the memory area L1. The bit line BL2 is coupled to the ground potential GND. The threshold voltage of the memory cell with the potentials of the bit lines thus set is large, when the data is written to the memory area L1.
Once the potentials of the bit lines are set, the word line WL1 is activated to H level of the read state. If the threshold voltage of the memory cell is lower than the H level of the read state, then the read current Ir1 flows from the bit line BL3 to the bit line BL2. By detecting the current value of this time with the sense amplifier circuit 12, whether the data has been written to the memory area L1 or not can be read out as information.
As described above, with respect to the memory area L1, directions of current at writing operation and reading operation are opposite.
FIG. 13 is a diagram related to a data writing operation to a memory area L2 of the memory cell 112.
Referring to FIG. 13, the bit line BL3 is provided with the write power source potential VddW and the bit line BL2 is coupled to the ground potential when writing data to the memory area L2. When the word line WL1 is activated to H level of the write state, write current Iw2 flows from the bit line BL3 to the bit line BL2. At this time, data is written to the memory area L2.
FIG. 14 is a diagram related to a data reading operation from the memory area L2 of the memory cell 112.
Referring to FIG. 14, the bit line BL2 is provided with the read power source potential VddR via the sense amplifier circuit 12 when reading data from the memory area L2. The bit line BL3 is coupled to the ground potential GND.
The threshold voltage of the memory cell with the potentials of the bit lines thus set is large, when the data is written to the memory are L2. When the threshold voltage of the memory cell is small, by activating the word line WL1 to the H level of the write state, the read current Ir2 flows from the bit line BL2 to the bit line BL3. By detecting the current value of this time with the sense amplifier circuit 12, whether the data has been written to the memory area L2 or not can be sensed.
As described above, with respect to the memory area L2 also, direction of current at writing operation and reading operation are opposite.
In the conventional NROM, when data reading is to be performed, bit lines are set to the floating state, except for the bit lines connected to the selected cell at both sides.
For example, when data are read from the memory cell 112, all transistors included in the switch units 531, 534 and 535 are set to be non-conductive. The bit lines Bl1, BL4 and BL5 are set at the floating state.
FIG. 15 is an operational waveform diagram related to data reading operation from the memory cell 112 shown in FIG. 10.
Referring to FIGS. 10 and 15, in order to precharge the bit lines BL1 to BL5 at 0V, control signals GG1 to GG5 are activated from L level to H level at time point t1, and control signals GG1 to GG5 are inactivated from H level to L level at time point t2. As a result, the bit lines BL1 to BL5 are in the floating state precharged at 0V.
Subsequently, a read memory cell is selected, and in order to perform data reading, the control signal VG3 is activated from L level to H level at time point t3. As a result, the N-channel MOS transistor 562 is rendered conductive to connect the bit line BL3 and the read power source line 524. Then, the bit line BL3 is provided with the read power source potential VddR via sense amplifier circuit 12.
Simultaneously, the control signal GG2 is activated from L level to H level. Then, the N-channel MOS transistor 554 is rendered conductive to connect the bit line BL2 to the ground power source line 522. As a result, the bit line BL2 is set at the ground potential GND. The potential of the node NA is set at the read power source potential VddR, and the potential of the node NB is set at 0V.
On the other hand, the word line WL1 is set at 0V and thus bit lines are not conductive with each other irrespective of the states of the memory cells 111 and 113. Therefore, the nodes NC and ND remain at the floating state being precharged at 0V.
In this state, at time point t4, the word line WL1 is activated from L level to H level. At this time, if charges are trapped in the memory area L1 of the memory cell 112, then the threshold voltage rises and hence no current flows from the node NA to the node NB. This state corresponds to the state storing data xe2x80x9c0xe2x80x9d.
If no charges are trapped in the memory area L1, then the threshold voltage will not rise, thus in response to the activation of the word line WL1, current flows from the node NA to the node NB. This state corresponds to the state storing data xe2x80x9c1xe2x80x9d. Accordingly, by sensing current with the current sense amplifier 12, data stored in the memory area L1 of the memory cell 112 can be determined.
FIG. 15 shows a state in which charges are trapped in the memory area L1 of the selected memory cell, and hence, not passing current. Actually, however, current flows thorough the sense amplifier circuit 12 for a certain period. Specifically, current flowing from the bit line BL3 to the bit line BL2 and the potential of the node ND gradually increases during a time period of t4 to t5. This is because the memory cells 113 and 114 are in a state not trapping charges in the memory areas, the bit lines BL4 and BL5 are coupled to the read power source potential VddR via these memory cells on activation of the word line WL1, and therefore charging is initiated.
FIG. 16 is a diagram related to charging of the node ND during the time period t4 to t5.
Referring to FIGS. 15 and 16, current does not flow through memory cell during the time period t4 to t5. This is because charges are trapped in the memory area L1 and hence the threshold voltage is increased even when the word line WL1 is activated to H level, thus the transistor is not rendered conductive.
In contrast thereto, charges are not trapped in the memory areas of the memory cells 113 and 114, and thus at these cells transistors are rendered conductive to pass the charging current to bit lines BL4 and BL5.
FIG. 17 shows time changes of current flowing through the sense amplifier circuit 12.
Referring to FIGS. 16 and 17, current as shown in a graph G11 flows through the sense amplifier circuit 12 when no charges are trapped in the memory area L1 and hence when data xe2x80x9c1xe2x80x9d is stored in the memory area L1. In this case, the current value is stabilized at once and thus no troubles arise.
On the other hand, when charges are trapped in the memory area L1 of the memory cell 112, bit lines BL3 to BL5 require a certain time period to complete the charging even though no current flows through the memory cell 12. The current sense amplifier circuit 12 cannot perform normal sensing operation until the charging current is stabilized. Depending on the sensing performance of the sense amplifier, given a reference value for determining the absence of current flow as approximately 2 xcexcA, about 25 ns of time from the initiation of sensing is required for a read operation.
As such, for reading data of xe2x80x9c0xe2x80x9d, a certain time period is required until the current value is stabilized, as shown in the graph G10.
An object of the present invention is to provide a non-volatile semiconductor memory device in which reading speed is improved.
In summary, the present invention provides a non-volatile semiconductor memory device including a first word line, a first to nth bit lines, first to nxe2x88x921th non-volatile memory cells, and a potential supply circuit.
As used herein, n is a natural number of at least 3, and m is a natural number smaller than n. The first to nth bit lines cross the first word line and are positioned successively in order. The first to nxe2x88x921th non-volatile memory cells are positioned respectively in nxe2x88x921 areas between the first and nth bit lines and connected to the first word line together.
Each of the first to n-xe2x88x921th non-volatile memory cells is connected between a higher order bit line and a lower order bit line which are two corresponding bit lines among the first to the nth bit lines. Each of the first to nxe2x88x921th non-volatile memory cells includes a memory transistor. The memory transistor has its control electrode connected to the first word line and stores one bit depending on whether a first current can flow or not from the higher order bit line to the lower order bit line on activation of the first word line. The memory transistor further stores the other bit depending on whether a second current can flow from the lower order bit line to the higher bit line on activation of the first word line.
The potential supply circuit, to check whether the first current flows through non-volatile memory cell, supplies ground potential to an mth bit line supplies a read power source potential higher than the ground potential to an m+1th bit line, and supplies a bias power source potential higher than the ground potential to an m+2th bit line independent of the read power source potential. The potential supply circuit includes a current sense circuit provided on a path through which the first current flows from the read power source potential to the ground potential for sensing the first current.
Therefore, the main advantage of the present invention is in achieving quick sensing of current to reduce the reading time, when adjacent memory transistors are rendered conductive in response to the activation of word line and no current flows through the read memory transistor.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.